Sunday, August 31, 2008

8-BIT Microcontroller

Features
· Compatible with MCS-51 Products · 4 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles · Fully Static Operation: 0 Hz to 24 MHz · Three-Level Program Memory Lock · 128 x 8-Bit Internal RAM · 32 Programmable I/O Lines · Two 16-Bit Timer/Counters · Six Interrupt Sources · Programmable Serial Channel · Low Power Idle and Power Down Modes

Pin Configurations PDIP/Cerdip
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4
Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51Ô instruction set and pinout.
The on-chip Flash allows the program memory to be reprogrammed in-system or by
a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU
with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.

The AT89C51 provides the following standard features: 4
Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock
circuitry. In addition, the AT89C51 is designed with static
logic for operation down to zero frequency and supports
two software selectable power saving modes. The Idle
Mode stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning.
The Power Down Mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until
the next hardware reset.

When the AT89C51 is executing code from external program
memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external program
memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable
voltage (VPP) during Flash programming, for parts that require
12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.

INTEL PROCESSOR Specifications..

INTEL PROCESSOR Specifications..

T9500 6MB L2 2.60 GHz 800 MHz
T9300 6MB L2 2.50 GHz 800 MHz
T8300 3MB L2 2.40 GHz 800 MHz
T8100 3MB L2 2.10 GHz 800 MHz
T7800 4 MB L2 2.60 GHz 800 MHz
T7700 4 MB L2 2.40 GHz 800 MHz
T7600 4 MB L2 2.33 GHz 667 MHz
T7500 4 MB L2 2.20 GHz 800 MHz
T7400 4 MB L2 2.16 GHz 667 MHz
T7300 4 MB L2 2 GHz 800 MHz
T7250 2 MB L2 2 GHz 800 MHz
T7200 4 MB L2 2 GHz 667 MHz
T7100 2 MB L2 1.80 GHz 800 MHz
T5750 2 MB L2 2 GHz 667 MHz
T5600 2 MB L2 1.83 GHz 667 MHz
T5550 2 MB L2 1.83 GHz 667 MHz
T5500 2 MB L2 1.66 GHz 667 MHz
L7500 4 MB L2 1.60 GHz 800 MHz
L7400 4 MB L2 1.50 GHz 667 MHz
L7300 4 MB L2 1.40 GHz 800 MHz
L7200 4 MB L2 1.33 GHz 667 MHz
U7700 2 MB L2 1.33 GHz 533 MHz
U7600 2 MB L2 1.20 GHz 533 MHz
U7500 2 MB L2 1.06 GHz 533 MHz

Friday, August 8, 2008

Northbridge

In the part "Northbridge", one will find the interface memory DDR. It is the first difference between different the processor from the family 64 bits from AMD. Athlon 64 manage an external data bus of 64 bits, the FX and Opteron of the data buses of 128 Bits. As these processors manage memories ECC, Athlon 64 bits will accept memory ECC on 8 bits of control against 16 bits-ECC for the others. The socket processor is thus different for the 64 and 64 FX.
Part JTAG - Debug is related to the difficulty in testing complex electronic circuits. This developed method fine of the Eighties makes it possible to test "outside" the electronic circuit by memorizing the values of entries and exits. It thus is not directly used in the PC.

Hyper transport is the fast bus allowing connection between northbridge and Southbridge. The number of channels is 1 for Athlon 64 and Athlon 64FX. For the opteron, it is of 3 channels. Each channel is able to transfer 3,2 GB/s in each direction (6,4 GB/s on the whole).

All this explains in particular different the socket for the family Athlon 64, Athlon 64: socket 754, advanced mid- 2004 towards the socket 939 which manages Dual Channel

Athlon 64 FX: socket 940 (identical to the opteron), advanced mid- 2004 towards the socket 939 (identical to Athlon64). First Athlon FX51 were thus of Opteron with 2 of the three channels hyper decontaminated transport. Athlon FX53 becomes again Athlon 64 (which it replaces) with a more important mask.

How Athlon 64 works?

In the preceding chapter, we have the internal architecture of standard processors. We will see in this chapter the architecture of Athlons 64 bits (Athlon 64 - Athlon FX and Opteron). Even if the heart of the processor seems equivalent, the various models differ mainly by their external components.

The athlon 64 in the general direction use a mixed internal architecture 32 - 64 bits. They are thus able to use operating systems 32 bits (Windows 95/98/me/2000/NT/XP) and operating system 64 bits (currently semi-2004: Linux even if a version Windows 64 bits is under development - specific versions Windows server).

Itanium of INTEL use only one architecture 64 bits, they can thus use only operating system 64 bits.

A processor 64 bits using an operating system 64 bits can jointly use applications 32 and 64 bits. On the other hand, case of the AMD, a processor 64 bits turning on an operating system 32 bits can make turn only of the applications 32 bits. Conversely, a processor 32 bits can use only operating systems and applications 32 bits.

A broad part of the information taken again on this page comes directly from the site of AMD.

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